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| CS5828 28:4 LVDS Transmitter GENERAL DESCRIPTION The CS5828 receives four sets of 7-bit data in CMOS logic level and converts them into four lowvoltage differential signaling (LVDS) serial channels. The 7-bit input data is referenced to the CKIN signal. The RF pin selects either rising or falling edge trigger of CKIN. Parallel to serial conversion is performed by a 7X internal generated clock reference using onchip PLL using CKIN. A copy of CKIN but phaselocked to the output serial streams, CLKOUT, is also converted to the fifth LVDS channel. The CS5828 offers a reliable communication media using LVDS signaling and provides low EMI dealing with wide, high-speed TTL interfaces. This is especially attractive for interfaces between GUI controller and display systems such as LCD panels for SVGA/XGA/SXGA applications. FEATURES * Four 7-bit serial and one clock LVDS channels. * Compatible with ANSI TIA/EIA-644 LVDS standard. * Wide CKIN ranges from 31MHz to 85MHz. * Fully integrated on-chip PLL that provides 7X CKIN serial shift clock. * Pin selectable for rising or falling edge trigger. * Support power-down mode. * 5V/3.3V tolerant data input. * Single 3.3V supply operation. * CMOS low power consumption. * Functional compatible with DS90C385. * Available in 56-pin TSSOP package. BLOCK DIAGRAM D0,D1,D2,D3, D4,D6,D7 DIN SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y0P EN Y0N D8,D9,D12,D13, D14,D15,D18 DIN SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y1P EN Y1N D19,D20,D21,D22, D24,D25,D26 DIN PARALLEL-IN SERIAL-OUT EN Y2P Y2N SHIFT/LOAD_N 7-Bit SHIFT REGISTER CLK D27,D5,D10,D11, D16,D17,D23 DIN SHIFT/LOAD_N CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER Y3P EN Y3N RF CKIN 7xCLK PHASE LOCK LOOP SHIFT/LOAD_N R/F CLK CKOP EN CKON SHTDN CONTROL LOGIC CS5828 Myson Century, Inc. Taiwan: No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 USA: 4020 Moorpark Avenue Suite 115 San Jose, CA, 95117 Tel: 408-243-8388 Fax: 408-243-3188 Sales@myson.com.tw www.myson.com.tw Rev.1.4 August 2002 page 1 of 13 CS5828 PIN CONNECTION DIAGRAM VDD D5 D6 D7 VSS D8 D9 D10 VDD D11 D12 D13 VSS D14 D15 D16 RF D17 D18 D19 VSS D20 D21 D22 D23 VDD D24 D25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D4 D3 D2 VSS D1 D0 D27 LVDS_VSS Y0M Y0P Y1M Y1P LVDS_VDD LVDS_VSS Y2M Y2P CKOM CKOP Y3M Y3P LVDS_VSS PLL_VSS PLL_VDD PLL_VSS SHTDN CKIN D26 VSS CS5828 Figure-1 56-pin TSSOP page 2 of 13 CS5828 PIN DESCRIPTION Name D0,D1,D2,D3,D4, D6,D7 D8,D9,D12,D13, D14,D15,D18 D19,D20,D21,D22 ,D24,D25,D26 D27,D5,D10,D11, D16,D17,D23 CKIN RF SHTDN I/O I I I I I I I Description Parallel data input for Y0 LVDS channel. D[0] is LSB and D[7] is MSB. MSB is shifted out first. Parallel data input for Y1 LVDS channel. D[8] is LSB and D[18] is MSB. Parallel data input for Y2 LVDS channel. D[19] is LSB and D[26] is MSB. Parallel data input for Y3 LVDS channel. D[27] is LSB and D[23] is MSB. Parallel input clock.This clock signal is used for parallel data reference. It is also used by the on-chip PLL to generate the 7X shift clock for parallel to serial conversion. Rise/fall select. This pin selects the polarity of the CKIN edge for data input. RF = 1 selects CKIN rise edge, and RF = 0 selects CKIN fall edge. Shutdown control (low active). When SHTDN is low, the internal PLL is put into inhibit mode and all LVDS output channels are shut off. This also resets all internal registers. For normal operation, SHTDN should be set to high. Y0 LVDS channel output. These are differential LVDS outputs for Y0 channel corresponds to D0, D1, D2, D3, D4, D6, D7. Y1 LVDS channel output. These are differential LVDS outputs for Y1 channel corresponds to D8, D9, D12, D13, D14, D15, D18. Y2 LVDS channel output. These are differential LVDS outputs for Y2 channel corresponds to D19, D20, D21,D22, D24, D25, D26. Y3 LVDS channel output. These are differential LVDS outputs for Y3 channel corresponds to D27, D5, D10, D11, D16, D17, D23. Clock LVDS channel output. These are differential LVDS output for the replica of CKIN signal. CKOP and CKON are derived from the internal phase lock loop and phase aligned with the serial data output and can be used by the LVDS receiver for reference edge. Power supply for PLL circuit. Power ground for PLL circuit. Power supply for output buffer circuits. Power ground for output buffer circuits. Power supply for internal circuits. Power ground for internal circuits. Y0P, Y0N Y1P, Y1N Y2P, Y2N Y3P, Y3N CKOP, CKON O O O O O PLL_VDD PLL_VSS LVDS_VDD LVDS_VSS VDD VSS P P P P P P page 3 of 13 CS5828 FUNCTIONAL DESCRIPTION Control logic There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are controlled by the control signal "SHTDN". If SHTDN is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. In the power down mode, every block is off to make sure the least power consumption. 7 x CLK PLL 7 x CLK PLL, which is a phase lock loop, generates seven times clock of CKIN. The signal "RF" indicates that the input data (D0 ~ D27) is rising edge or falling edge trigger by CKIN. If RF=1, it is rising edge trigger, else if RF=0, it is falling trigger. This seven times clock of CKIN is used by the Parallel ~ LOAD 7 Bit shift Register. 7 x CLK PLL also generate the control signal "SHIFT/LOAD". This signal is also used by the Parallel ~ LOAD 7 Bit Shift Register to indicate when to load data or shift data. Parallel ~ LOAD 7 Bit shift Register This block transfers 7 bits parallel data into one bit series data out. It is controlled by SHIFT/LOAD. If this control signal is low, the data are loaded into shift registers. Next, the SHIFT/LOAD turns high to shift data from shift register to output buffer seven times. One load and then seven shift. Ref: There are two properties in this block. One is that it supports reference voltage to fine the output's common mode voltage. Another is that it generates about (4ns ~6ns) pulse width's power on reset signal. When power on, all block would be reset by power on reset signal to make sure that the circuit would not stuck-at some situation we do not care. Output buffer There are four data output buffers and one clock output buffer. Output buffer generates differential pair output that swing is under 500 ~ 900mV, and common-mode voltage is under 1.125V ~ 1.375V. page 4 of 13 CS5828 RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL ZL TA Supply voltage High-level input voltage Low-level input voltage Differential load impedance Operating free-air temperature Parameter Min 3 2 90 0 Typ 3.3 Max 3.6 0.8 132 70 Unit V V V C TIMING REQUIREMENTS Symbol tC tW tt tsu th Input clock period Pulse duration, high-level input clock Transition time, Input signal Setup time, data, D0~D27 valid before CKIN (RF = 0) or CKIN(RF = 1) Hold time, data, D0~D27 valid after CKIN (RF = 0) or CKIN(RF = 1) 3 1.5 Parameter Min 11.76 0.4tC Typ Max 32.4 0.6tC 5 Unit ns ns ns ns ns page 5 of 13 CS5828 DC CHARACTERISTICS Symbol VIT VOD VOD VOC(SS) VOC(PP) IIH Parameter Input threshold voltage Differential steady-state output voltage magnitude Change in the steady-state differential output voltage magnitude between opposite binary states Steady-state common-mode output voltage Peak-to-peak common-mode output voltage High-level input current Condition Min - Typ 1.4 340 10 80 40 Max 454 50 1.375 150 20 10 10 24 12 10 250 60 Unit V mV mV V mV A A A mA mA A A mA RL = 100 247 1.125 - VIH = VCC - IIH-SHTDN High level input current for SHTDN pin VIH = VCC IIL IOS IOZ ICC(AVG) Low-level input current Short-circuit output current High-impedance output current Quiescent supply current (average) VIL = 0 VO(Yn) = 0 VOD = 0 VO = 0 to VCC Power down SHTDN = 0 Enabled, RL = 100 (4 places) Gray_scale pattern VCC = 3.3V, tC = 11.76ns Enabled, RL = 100 (4 places) Worst_case pattern tC = 11.76ns CI 50 75 mA Input capacitance 3 - pF Note: All typical values are at VCC = 3.3V, TA = 25C. page 6 of 13 CS5828 AC CHARACTERISTICS Symbol t0 t1 t2 t3 t4 t5 t6 tskew tc(o) tw tt tenable tdisable Parameter CKO to bit 0 CKO to bit 1 CKO to bit 2 CKO to bit 3 CKO to bit 4 CKO to bit 5 CKO to bit 6 Output skew Cycle time, Output clock jitter Pulse duration, high-level output clock Transition time, differential output voltage (tr or tf) Enable time, SHTDN to phase lock (Yn valid) Disable time, SHTDN to off state (CKO low) Condition Tc= 11.76 ns Min -0.2 1/7tc-0.2 2/7tc-0.2 3/7tc-0.2 4/7tc-0.2 5/7tc-0.2 6/7tc-0.2 Typ 0 Max 0.2 1/7tc+0.2 2/7tc+0.2 3/7tc+0.2 4/7tc+0.2 5/7tc+0.2 6/7tc+0.2 Unit ns ns ns ns ns ns ns ns ps ns ps ms ns 100 4/7tc -0.2 260 - 0.2 1500 - 700 1 250 page 7 of 13 CS5828 tsu th Dn CKIN (RF=0) CKIN (RF=1) Note: Maximum value of tr, tf = 5ns Figure-2 Setup and Hold Time Definition YP VOD 49.91%(2 Places) VOC YM CL=10pF Max (2 Places) (a) SCHEMATIC 100% VOD(H) VOD(L) tr 80% 0V 20% 0% tf VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure-3 Test Load and Voltage Definitions for LVDS Outputs page 8 of 13 CS5828 TEST PATTERN CKIN D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4-7, 12-15, 20-23 D24-27 Figure-4 16-Grayscale Testing Pattern Waveforms CKIN Even Dn Odd Dn Figure-5 The Worst-case Testing Pattern Waveforms CKO t0 Yn t1 t2 t3 t4 t5 t6 Figure-6 Timing Waveform's Definitions page 9 of 13 CS5828 TYPICAL CHARACTERISTICS CKIN SHTDN tenable Yn Invalid valid valid valid Note: RF=1 Figure-7 Enabled Time Waveforms CKIN CKO tdisable SHTDN Note: RF=1 Figure-8 Disabled Time Waveforms page 10 of 13 CS5828 PACKAGE OUTLINE (56-pin TSSOP) D c E1 E L A2 A1 e b A Symbol A A1 A2 b c D E E1 e L Dimensions in Millimeters MIN 1.05 0.05 0.17 0.09 13.90 7.80 6.00 0.50 0 NOM 0.90 0.20 0.15 14.00 8.10 6.10 0.50 MAX 1.20 0.15 0.27 0.20 14.10 8.40 6.20 0.75 7 Dimensions in Inches MIN 0.041 0.002 0.007 0.004 0.547 0.307 0.236 0.020 0 NOM 0.035 0.008 0.006 0.551 0.319 0.240 0.0197 MAX 0.047 0.006 0.010 0.008 0.555 0.330 0.244 0.030 7 Note: The CS5828 products keep using the original Century logo. page 11 of 13 CS5828 PACKAGING SPECIFICATION P0 T1 B P2 B D0 A E R0.3MAX 3.4 B0 3.0 2.0 3.0 F W 6.0 6.8 Section A-A 8.6 K1 T2 Chamfer R0.1 P1 D0 A R0.3 Typical Section B-B Dimension Symbol Unit: mm B0 14.5 D0 1.5 +0.1 -0 E 1.75 0.1 F 11.5 0.05 K1 1.3 Max P0 4 0.2 P1 12.0 0.1 P2 2 0.05 T1 0.3 0.05 T2 1.8 Max W 24.0 0.3 Standard Packing Quantity Carrier Tape Width 24mm Reel Size 330mm Pocket Pitch 4mm Leader No. of Pockets 20 End No. of Pockets 30 Quantity (Pcs/Reel) 2500 Reel For Taping W1 D B E C A W2 Unit: mm A 330 +1 -4 B 100 0.1 C 13 +0.5 -0.2 D 20.2 0.8 E 2.0 0.5 W1 24.8 +0.3 -0.2 W2 30.2 Max page 12 of 13 CS5828 Leader Part And Taped End Leader Part Tape End Pin1 20 Vacant position 0 Top cover tape 30 Vacant position Unwinding Direction Approval Supplier For Packing Material Item Carrier Tape Cover Tape Plastic Reel Supplier ADVANTEK ADVANTEK ADVANTEK Ordering Information Part Number Prefix CS Part Type 5828 Package Type N:TSSOP page 13 of 13 |
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